One of the most useful on-chip application specific integrated circuit (ASIC) components is the static RAM, which is employed as local memory, register file and buffers.
To test the RAM cells in VLSI designs, as well as other logic, many different functional and test strategies may be used. D-algorithm (DDrive) is one of the methods commonly used. In fact, the RAM cell used here has the DDriveability feature in it. DDrive is a deterministic test scheme and many vectors have to be generated for a good fault coverage.
Any functional test is not too different in nature from DDrive testing. In either case, a test vector, to check for specific faults, has to be shifted into the RAM snake (all flip-flops are connected to each other as a long shift register), and one clock is applied and the result of the test is shifted out. This procedure is repeated for each test vector generated.
The shift process requires many clocks, considering the quantity of vectors that are generated (about 10,000 vectors for the RAM used here). Manual generation of test vectors for functional testing requires understanding of the functionality of the circuit and is very time-consuming.
No current VLSI design has RAM cells with self-test capabilities. Mostly, functional testing has been used.
The object of this invention is to provide a circuit for a RAM supercell so that the RAM will be self-testable by generating patterns and collecting signatures using flip-flops existing in the RAM cell. Test of the RAM will be possible in a more systematic way and in a much shorter time. Further, only a few test vectors will have to be shifted in.